Conventional nonvolatile semiconductor memory elements are available, depending on the application, in a plurality of different designs, for example PROM, EPROM, EEPROM, FLASH EEPROM, SONOS, etc. These different designs differ in particular in the erasure option, programmability and programming time, retention time, memory density and their manufacturing costs. There is a particular need for high-density and economical flash semiconductor memories. Known designs are, in particular, what are referred to as NAND and ETOX memory cells whose memory density however requires more than 4F2, F being the smallest structural dimension of the semiconductor memories occurring in the process. In the publication by B. Eitan et al. “NROM: A novel localized trapping, 2-bit nonvolatile Memory Cell”, IEEE Electron Device Letters vol. 21, No 11, November 2000, what is referred to as an NROM memory is described, which, by using a 2-bit cell, makes possible a memory cell with a 2F2 surface density.
However, all the nonvolatile memory elements mentioned above require comparatively high voltages of at least 10 V for programming or erasing the bits stored in a memory layer. For example, an NROM memory cell has to function with gate voltages in the region of 9 V. Since external voltages of 10 V or more are not available in the typical fields of application of flash memory elements, such voltages must be generated “on-chip”. Although the charge pumps necessary for this are generally known, they require a considerable amount of surface area on the memory chip, thus reducing its degree of integration and consequently disadvantageously increasing the manufacturing costs.
There is a perceived need for a semiconductor memory having a plurality of memory cells which requires, in particular, relatively low programming voltages and permits a high-density memory cell array.